My Publications

Peer Reviewed Articles

• Designing Neural Synthesizers for Low Latency Interaction
  Franco Caspe, Jordie Shier, Mark Sandler, Charalampos Saitis, Andrew McPherson
  Journal of the Audio Engineering Society

• Shifting Ambiguity, Collapsing Indeterminacy: Designing with Data as Baradian Apparatus
  Courtney N. Reed, Adan L. Benito, Franco Caspe, Andrew P. McPherson.
  ACM Transactions on Computer-Human Interaction

• FM Tone Transfer with Learned Envelopes
  Franco Caspe, Andrew McPherson, Mark Sandler.
  Audio Mostly 2023

• Differentiable Modelling of Percussive Audio with Transient and Spectral Synthesis
  Jordie Shier, Franco Caspe, Andrew Robertson, Mark Sandler, Charalampos Saitis, Andrew McPherson.
  Forum Acusticum 2023

• DDX7: Differentiable FM Synthesis of Musical Instrument Sounds
  Franco Caspe, Andrew McPherson, Mark Sandler.
  23rd International Society for Music Information Retrieval Conference (ISMIR 2022)

• Real-time FM tone transfer with Bela
  Franco Caspe, Andrew McPherson, Mark Sandler.
  Workshop on Embedded AI For NIME. Held at NIME 2022

• Metasurface based pattern reconfigurable antenna for 2.45 GHz ISM band applications.
  Janapala, Doondi Kumar, Caspe, Franco S., Moses, Nesasudha.
  International Journal of RF and Microwave Computer-Aided Engineering

• Gateway for data transferring between real time and deferred time domains. Franco S. Caspe et al.
  Proceedings of “VIII Congreso de Microelectrónica Aplicada”

• A real time F0 estimator based on the YIN algorithm.
  Franco S. Caspe et al. Proceedings of CASE 2017 ISBN: 978-987-46297-3-9.

• A real-time network interface test bench.
  Franco S. Caspe et al.
  Proceedings of CASE 2016 ISBN: 978-987-45523-8-9. Outstanding work mention.

Erasmus Mundus Master’s in Computer Vision (IPCV) Thesis

• Efficient DNN Serving.
  Defended at Peter Pazmany Catholic University.

Electronic Engineering Thesis

• A real-time network test-bench for multiple communication interfaces. Published in Spanish, at UTN’s repository.

Other articles

• Baking a custom BNN for the Zybo-Z7. How to implement Xilinx’s Binary Neural Network streaming architecture with the smallest FPGA in the market.